This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-026226, filed Feb. 3, 2003, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and in particular, to a semiconductor integrated circuit device having a vertical type bipolar transistor.
2. Description of the Related Art
In a semiconductor integrated circuit (IC) device having a bipolar transistor formed on a semiconductor substrate, a diffusion region is formed around the bipolar transistor in order to electrically isolate the transistor from other transistor elements (not shown).
FIG. 5 is a cross-sectional view showing the basic structure of the transistor formed on the semiconductor substrate. As seen from FIG. 5, an N-type diffusion region (first diffusion region) tub for electric isolation is formed in a P-type semiconductor substrate sub forming an IC. A vertical type bipolar transistor Q1 is formed in the diffusion region tub. That is, a p-type diffusion region (second diffusion region) c is formed in the diffusion region tub, and an N-type diffusion region (third diffusion region) b is formed in the diffusion region c, and further, a P-type diffusion region (fourth diffusion region) e is formed in the diffusion region b. An electrode TUB, collector electrode C, base electrode B and emitter electrode E are formed on the semiconductor substrate sub in the diffusion region tub, diffusion region c, diffusion region b and diffusion region e, respectively. A substrate electrode SUB is formed on the semiconductor substrate sub outside the above diffusion regions.
A voltage is applied to the diffusion region tub and the diffusion region c and the semiconductor substrate sub so that each PN junction between the diffusion region tub and diffusion region c and between the diffusion region tub and the semiconductor substrate sub are reverse-biased. By doing so, the semiconductor substrate sub and the diffusion region c are electrically isolated.
As shown in FIG. 5, parasitic transistors (hereinafter, referred simply to as transistor) Q2 and Q3 and a distributed resistor (hereinafter, referred simply to as resistor) r are formed by the diffusion region tub, the diffusion region c, the diffusion region b and the diffusion region e. The transistor Q1, the transistor Q2, the transistor Q3 and the resistor r form an equivalent circuit shown in FIG. 6. The transistor Q2, the transistor Q3 and the resistor r are formed, thereby causing the following problem in accordance with biasing to the diffusion region tub.
As depicted in FIG. 7, for example, the highest potential of IC, that is, a potential (typically, power-supply potential) Vcc is applied to the electrode TUB. By doing so, each PN junction formed between the diffusion region tub and the diffusion region c and between the diffusion region tub and the semiconductor substrate sub is always reverse-biased. However, the above biasing is not used if the breakdown voltage between the diffusion region c and the diffusion region tub is low. In addition, if the collector electrode C is connected to an external device, there is a possibility that a potential more than the above potential Vcc is applied to the collector electrode C. As a result, the junction between the electrode TUB and the collector electrode C is forward-biased; therefore, large current flows through the electrode TUB in the forward direction of a diode d. For this reason, the PN junction between the diffusion region tub and the diffusion region c is broken down, and an excessive load is given to the device connected with the collector electrode C.
Another biasing to the diffusion region tub is employed such that the electrode TUB and the collector electrode C are connected as shown in FIG. 8. According to the above biasing, the diffusion region tub and the diffusion region b have the same potential; for this reason, the PN junction between the diffusion region tub and the diffusion region b is not tuned on even if a potential more than the potential Vcc is applied to the collector electrode C. Therefore, it is possible to prevent excessive current from flowing through the transistor Q1. However, according to the above biasing, the transistor Q1 and the transistor Q2 form a thyristor structure; for this reason, latch-up is easy to occur. More specifically, when a collector current of the transistor Q1 becomes a predetermined value with the operation of the transistor Q1, the transistor Q2 is turned on by the potential difference generated across the resistor r. As a result, a collector current of the transistor Q2, that is, a base current of the transistor Q1 increases, thereby increasing a current carrying the collector-emitter junction of the transistor Q1. According to the above positive feedback, a large current flows through the transistor Q1; for this reason, there is a possibility that the transistor Q1 is broken down.
Another biasing is employed such that a resistor element R is interposed between the electrode TUB and the collector electrode C as shown in FIG. 9. According to the above biasing, in the above latch-up operation process, the current becomes hard to flow between the collector and the emitter of the transistor Q2; therefore, the latch-up is prevented. The larger the value of the resistor element R is, more effective it is to prevent the latch-up. However, too large value of the resistor element R causes the following problem. That is, as shown in FIG. 10, when the transistor Q1 is saturated, the potential high and low relationship between the electrode B and the electrode TUB is inverted followed by inversion of a bias direction of the transistor Q2, which causes the emitter and collector of the transistor Q2 to operate in a inverted state of the those of the FIG. 5. As a result, the current flows from the collector of the transistor Q2 to the emitter thereof. However, because the value of the resistor element R is large, the collector potential of the transistor Q2 decreases. Therefore, the transistor Q2 is saturated. Whereupon, the base-emitter junction of the transistor Q3 is forward-biased, so that the transistor Q3 can be turned on. The transistor Q3 is turned on; as a result, the collector current of the transistor Q1 flows into the semiconductor substrate via the transistor Q3 (substrate current Isub). In particular, because the transistor Q3 has a large area on the substrate plane, it is easy to turn on even if the bias of the base-emitter junction is small. As a result, the above problem remarkably appears.
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a first conduction type semiconductor substrate; a second conduction type first diffusion region formed in a surface of the semiconductor substrate; a first conduction type second diffusion region formed in the first diffusion region; a second conduction type third diffusion region formed in the second diffusion region; a first conduction type fourth diffusion region formed in the third diffusion region; a current measuring section measuring a current value of current flowing through the second diffusion region, and outputting a current value signal in accordance with the measured current value; a control section supplied with the current value signal, and supplying control current to the first diffusion region in accordance with the current value signal; and a first resistor element having a first terminal connected with the first diffusion region, and a second terminal connected with the second diffusion region.
According to a second aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a first conduction type semiconductor substrate; a second conduction type first diffusion region formed in a surface of the semiconductor substrate; a first conduction type second diffusion region formed in the first diffusion region; a second conduction type third diffusion region formed in the second diffusion region; a first conduction type fourth diffusion region formed in the third diffusion region; a current measuring section measuring a current value of current flowing through the fourth diffusion region, and outputting a current value signal in accordance with the measured current value; a control section supplied with the current value signal, and supplying control current to the first diffusion region in accordance with the current value signal; and a first resistor element having a first terminal connected with the first diffusion region, and a second terminal connected with the second diffusion region.